Thin film transistors are field effect transistors (FETs) that offer major cost and density advantages. However, TFTs have some inferior characteristics such as lower gains and higher off-state leakage currents. Unlike the conventional FETs where the source, drain and channel regions are formed in the body of a single crystal substrate, the device regions of a TFT are formed in a polysilicon or an amorphous silicon layer (device layer) overlying a substrate. Since the polysilicon layer is formed at relatively lower temperatures and need not be in the body of the single crystal substrate, the device regions can be formed above the substrate to form stacked transistors, an advantage which provides greater density and lower cost. The TFTs are most commonly used in flat panel displays as switching transistors and in Static Random Access Memories (SRAM) as load devices. Because the device polysilicon layer (channel layer) is not part of the substrate 5, the gate insulator 7 and electrode 6 can be positioned over the channel layer 8 (Top-Gate TFT) as shown in FIG. 1A, or under the channel layer 8 (Bottom -Gate TFT) as shown in FIG. 1B. Whereas both top-gated and bottom-gated TFTs have been used in SRAMs, bottom-gated TFTs are more popular as they lead to greater packing density. The conventional bottom-gated TFT suffers disadvantages from (i) requiring an extra mask since source and drain regions are defined by lithography masking techniques and, (ii) drain off-sets that are lithographically defined and hence not self-aligned and symmetrical. This causes inconsistent "on" and "off" currents. Drain off-sets are a desired feature in TFTs and are simply lightly doped regions placed outside the edge of the gate conductor, somewhat similar to lightly doped drains (LDDs) in FETs. Drain off-sets reduce punch-thru problems and reduce the off-state leakage current.
Hayden et al., teach in U.S. Pat. No. 5,158,898, a method to form self-aligned bottom-gated TFT, which is shown in FIG. 2. Referring to FIG. 2, Hayden et al. form a stacked structure consisting of a gate electrode 16 and a gate insulator 26 and a sacrificial layer (not shown). By depositing and planarizing, insulator regions 22 are formed between the stacked structures. The sacrificial layer is removed to provide recessed gate regions 13 and 15. A polysilicon layer 28 (device layer) is deposited in the recess in a conformal manner and a dielectric layer 30 is deposited over layer 28. The remaining recess region is covered with a plug 32 which can be insulating such as spin-on glass or conducting such as polysilicon. An implantation is used to selectively dope the device layer not covered by the plug 32 to create the source/drain regions. The vertical segments of the polysilicon layer 37 are considered off-set regions, the region below the plug 28 is the channel region and is controlled by gate oxide 26. This process provides a self-aligned bottom-gated TFT, but involves many process steps that are difficult to control. In an alternate embodiment (not shown), the insulator 22 act as dopant source to the source and drain regions but prevented from doping the off-set regions by use of a diffusion barrier lining not shown. This process is equally complicated as the formation of device structure and dopant source involve controlled planarization and many process steps. This approach is not preferred for applications where low cost and low complexity are desired.
Another major interest in TFTs is to build vertically stacked GATE MOS device. U.S. Pat. No. 4,488,348 issued to Richard Jolly, teaches a method that is very cumbersome and involves polycrystalline silicon deposition, laser recrystallization, ion implantation and out-diffusion from a dopant layer. The resultant structure is quite complex.
U.S. Pat. No. 4,603,468 issued to H. W. Lam teaches formation of a single gate device to address underlying n-channel and overlying p-channel. The process involves conformally depositing a layer of doped oxide over the gate region, followed by etching back (with a planarizing layer) to remove the doped glass layer from above the gate region. A polycrystalline layer is deposited over this structure and by diffusion annealing the p-channel device is doped where it is in contact with the doped glass and not over the gate region. This process is somewhat similar to the Hayden et al.'s alternate embodiment process and suffers from difficulty to control etch-back planarization of very thin layers and steps (the gate height). Further, there is no provision for the formation of an off-set region in this process.
U.S. Pat. No. 4,628,589 issued to R. Sundaresan is somewhat similar to the Lam's process, except in this approach, the p-channel layer is first deposited conformally over the gate, followed by a deposition of doped glass layer, etch back to remove the doped glass from over the gate region and followed by annealing at a high temperature. Thus, only the source and drain regions in the polycrystalline layer are doped from the dopant containing layer from the top. No provision is made in this process for forming the off-set regions. The Sundaresan process also suffers from processes difficult to control, similar to the Lam process.
Thus, there is a clear need in TFT manufacturing for a simplified and high yielding process, that is self -aligning, allows for the formation of off-set regions and involves fewer, easily controllable manufacturing steps.